Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Locally ion-implanted JFET in an InGaAs/InP p-i-n photodiode layer structure for a monolithically planar integrated receiver OEIC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Bauer, J.G. ; Siemens Res. Lab., Munchen, Germany ; Albrecht, H. ; Hoffmann, L. ; Romer, D.
more authors

A novel planar concept for the monolithic integration of a p-i-n photodiode (PD) and a junction field-effect transistor (JFET) is described. In an otherwise optimized InGaAs/InP PD layer sequence, grown by metalorganic vapor-phase epitaxy (MOVPE), a local Si- and Be-ion implantation has been performed to realize a thin n/sup +/-doped channel layer and a buried p-layer for the JFET. JFETs (1.6*290 mu m) have a maximum transconductance of 100 mS/mm and a cutoff frequency of 7 GHz. PDs with 64- mu m diameter show a dark current of 1 nA at -10 V, a responsivity of 1.1 A/W, and a 3-dB bandwidth of 7.6 GHz. The PD-JFET combination exhibits a clear open eye pattern at 200 Mb/s. A receiver sensitivity of -35 dBm for a bit error rate of 10/sup -9/ is estimated.<>

Published in:

Photonics Technology Letters, IEEE  (Volume:4 ,  Issue: 3 )