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Records of the 2003 IEEE International Workshop on Memory Technology, Design and Testing

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The following topics are dealt with: application specific DRAMs; cost optimum embedded DRAM design; memory test generation for DRAM defects; linked faults analysis in RAMs; reducing test time of embedded SRAMs; testability-driven optimizer and wrapper generator for embedded memories; ITRS commodity roadmap; electrical simulation model for the Chalcogenide phase-change memory cell.

Published in:

Memory Technology, Design and Testing, 2003. Records of the 2003 International Workshop on

Date of Conference:

29-29 July 2003