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JFET front-end circuits integrated in a detector-grade silicon substrate

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10 Author(s)
M. Manghisoni ; Ist. Nazionale di Fisica Nucl., Pavia, Italy ; L. Ratti ; V. Re ; V. Speziali
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This paper presents the design and experimental results relevant to front-end circuits integrated on detector-grade high resistivity silicon. The fabrication technology is made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy and allows using a common substrate for different kinds of active devices, such as N-channel JFETs and MOSFETs, and for pixel, microstrip, and PIN detectors. This research activity is being carried out in the framework of a project aiming at the fabrication of a multichannel mixed analog-digital chip for the readout of solid-state detectors integrated in the same substrate. Possible applications are in the field of medical and industrial imaging and space and high energy physics experiments. An all-JFET charge sensitive amplifier, which can use either a resistive or a nonresistive feedback network, has been characterized. The two configurations have been compared to each other, paying particular attention to noise performances, in view of the design of the complete readout channel. Operation capability in harsh radiation environment has been evaluated through exposure to γ-rays from a 60Co source.

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IEEE Transactions on Nuclear Science  (Volume:50 ,  Issue: 4 )