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Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application

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4 Author(s)
Kyu-Hyoun Kim ; DRAM Dev., Samsung Electron., Hwasung, South Korea ; Geun-Hee Cho ; Jung-Bae Lee ; Soo-In Cho

This paper describes DLL (delay locked loop) with built-in DCC (duty cycle correction) capability using a newly proposed coded phase blending scheme. The proposed scheme dramatically improves the DCC range and also enhances the total DLL performance. The DLL has been designed and fabricated within 1G-bit DDR (double data rate) synchronous DRAM using 0.11 /spl mu/m process and the measurement data show that it has unlimited DCC range, faster turn-on speed and smaller jitter compared with our previous work (2001).

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003