Cart (Loading....) | Create Account
Close category search window
 

A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yamasaki, T. ; Dept. of Electron. Eng., Tokyo Univ., Japan ; Fukuda, T. ; Shibata, T.

Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated 6 mW operation at 3 V power supply and the chip rate of 5 MS/S, while occupying the chip area of 1.0 mm/sup 2/.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.