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This paper describes an investigation of cosmic-ray-induced multi-cell error (MCE) behavior in SRAMs through device- and circuit-level simulation methods developed on the basis that a parasitic bipolar effect is responsible for such errors. The first demonstration that the maximum number of cell errors per cosmic-ray strike depends on the number of cells between well contacts (Nc) is presented. The results are applied in an error checking and correction (ECC) design guideline for the handling of cosmic-ray-induced multi-cell errors. A new architecture is proposed, in which matching of addresses to memory cells is consideration of the Nc. This architecture reduced soft error rate (SER) for an SRAM fabricated by using 0.13-/spl mu/m CMOS technology by 88%.