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A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias

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5 Author(s)
Bhavnagarwala, A.J. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Kosonocky, S.V. ; Immediato, M. ; Knebel, D.
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New SRAM circuit techniques implemented in a standard 0.13 /spl mu/m bulk Si CMOS process are reported in this work that (i) enable pico-joule energy dissipation per accessed bit at 1 GHz, (ii) lower total leakage power by over 80% from all unaccessed cells, during both active and standby modes, using a rigorous, self reverse biasing scheme that addresses leakage due to quantum tunneling and thermal excitation in all cell transistors, with an area, performance and noise margin penalty of less than 3% each and (iii) enable a programmable leakage reduction option that lowers leakage by over 90% when stored data is no longer desired.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003

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