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A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

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6 Author(s)
Hsu, S. ; Intel Labs., Intel Corp., Hillsboro, OR, USA ; Chatterjee, B. ; Sachdev, M. ; Alvandpour, A.
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This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003