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An adaptive reference generation scheme for 1T1C FeRAMs

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4 Author(s)
Chandler, T. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Sheikholeslami, A. ; Masui, S. ; Oura, M.

A reference time, instead of a reference voltage, is generated used to compare stored "0" and "1" in a race of bitlines towards reaching a threshold voltage in a 1T1C FeRAM. The reference time is adaptive, tracking process variations, aging, and fatigue of ferroelectric capacitors. This scheme is implemented in a 256/spl times/128-bit testchip in a 0.35 /spl mu/m ferroelectric process and achieves a 40 ns access time at 3 V.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003