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A 10-mW 3.6-Gbps I/O transmitter

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4 Author(s)
Hatamkhani, H. ; California Univ., Los Angeles, CA, USA ; Koon-Lun Jackie Wong ; Drost, R. ; Chih-Kong Ken Yang

This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003

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