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A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture

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5 Author(s)
Noda, H. ; ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan ; Inoue, K. ; Mattausch, H.J. ; Koide, T.
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A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003