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A 0.9 V 9 mW 1MSPS digitally calibrated ADC with 75 dB SFDR

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3 Author(s)
Dong-Young Chang ; ECE Oregon State Univ., Corvallis, OR, USA ; Gil-Cho Ahn ; Un-Ku Moon

A low-voltage two-stage algorithmic ADC incorporating the Opamp-Reset Switching Technique (ORST) is presented. The low-voltage digital CMOS process compatible operation is achieved without the clock boosting/bootstrapping or switched-opamp. The ADC employs a highly linear input sampling circuit at the front-end, and the digital output is calibrated using a radix-based scheme. The prototype was fabricated in a 0.18-/spl mu/m CMOS technology and the active die area is 1.2 mm/spl times/1.2 mm. The calibrated ADC demonstrates 75 dB SFDR at 0.9 V and 80 dB SFDR at 1.2 V. The total power consumption of the ADC is 9 mW at the clock frequency of 7 MHz (1MSPS).

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003