Cart (Loading....) | Create Account
Close category search window
 

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Nosaka, H. ; NTT Photonics Lab., NTT Corp., Tokyo, Japan ; Sano, E. ; Ishii, K. ; Ida, M.
more authors

We present a 40-Gbit/s-class clock and data recovery (CDR) circuit with a new lock detector. The lock detector operates robustly with a linear-type phase detector. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40, 43, and 45-Gbit/s PRBS with a length of 2/sup 31/-1. By attaching a frequency search and phase control (FSPC) circuit to the chip, the CDR circuit pulls in throughout a 39-45 Gbit/s range. The fabricated IC dissipates 1.89 W at a supply voltage of -4.5V.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.