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Clock generation and distribution for the third generation Itanium/spl reg/ processor

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3 Author(s)
Tam, S. ; Intel Corp., Santa Clara, CA, USA ; Desai, U. ; Limaye, R.

The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.

Published in:

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

12-14 June 2003

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