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Nine-metal-level (9 ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300 mm wafers for 90/65 nm generation has been successfully demonstrated for the first time. To minimize line-line capacitance for least BEOL interconnect RC delay, no higher-k cap for Cu CMP or higher-k middle etch stop layers for metal trench etching were used in inter metal dielectric (IMD) film stacking. Integration challenges in the Cu/LK (k=2.2) damascene building were overcome by novel approaches in IMD film processing, Cu CMP and patterning. Excellent physical, electrical, reliability, and packaging results from this Cu/LK (k=2.2) BEOL interconnects are demonstrated.