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Ultra-thin strained-SOI CMOS for high temperature operation

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7 Author(s)
T. Maeda ; Adv. Semicond. Res. Center, Nat. Inst. of Ind. Sci. & Technol., Kawasaki, Japan ; T. Mizuno ; N. Sugiyama ; T. Tezuka
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We have investigated mobility behaviors of ultra-thin strained-Si channel in fully-depleted (FD) strained-SOI CMOS at high temperature, which is a realistic chip operation condition. Although the decrease in the mobility enhancement with a decrease in strained-Si thickness determines the lower limit of strained-Si thickness, we have found that this lower limit becomes thinner at temperatures higher than room temperature. This is because the mobility degradation by the quantum-mechanical confinement (QMC) effect and MOS interface charges is relaxed at higher temperatures. This fact means that strained-SOI CMOS with thinner strained Si films, advantageous in terms of short channel effects, is acceptable under the real operation conditions.

Published in:

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

10-12 June 2003