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Robust process integration of 0.78 /spl mu/m/sup 2/ embedded SRAM with NiSi gate and low-K Cu interconnect for 90 nm SoC applications

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17 Author(s)
Kim, Y.W. ; Technol. Dev., Samsung Electron., Kyunggi-Do, South Korea ; Ahn, J.H. ; Park, T.S. ; Oh, C.B.
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The smallest high density embedded 0.78 /spl mu/m/sup 2/ 6T-SRAM cell for high performance 90 nm SoC applications was successively integrated by using leading edge technologies such as 193 nm ArF lithography, 1.2 nm gate oxide, 50 nm transistor and Cu dual damascene with low-K dielectric. Fully working for SRAM shows the SNM value above 200 mV. Device current of 870 /spl mu/A//spl mu/m and 390 /spl mu/A//spl mu/m for NMOS and PMOS respectively is achieved at 1.0 V operation. Reliability life time on hot carrier immunity shows more than 10 years.

Published in:

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

10-12 June 2003