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A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

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43 Author(s)
Arnaud, F. ; STMicroelectron., Crolles, France ; Boeuf, F. ; Salvetti, F. ; Lenoble, D.
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This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.

Published in:

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

10-12 June 2003