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Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

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11 Author(s)
Tsai, W. ; Intel Corp., IMEC, Leuven, Belgium ; Ragnarsson, L. ; Chen, P.J. ; Onsia, B.
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Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained. Sputtered TiN gate on the identical stacks yielded 0.82 nm EOT on NMOS devices using scaled chemical oxide interface with leakage current of 10/sup -3/ A/cm/sup -2/. CV hysteresis of TiN/HfO/sub 2/ was observed to decrease by an order of magnitude from the as deposited value to <10 mV after a 900/spl deg/C N/sub 2/ anneal.

Published in:

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Date of Conference:

10-12 June 2003