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Statistical bin limits-an approach to wafer disposition in IC fabrication

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2 Author(s)
Illyes, S. ; Intel Corp., Rio Rancho, NM, USA ; Baglee, D.A.G.

The authors describe the methodology of selecting and implementing statistical bin limits at wafer level test so as to minimize the value added to a defective product, improve the overall outgoing quality and reliability of a product, and provide a tool for helping to drive root cause identification of fabrication problems

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:5 ,  Issue: 1 )

Date of Publication:

Feb 1992

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