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Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits

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2 Author(s)
Tadepalli, Rajappa ; Dept. of Mater. Sci. & Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA ; Thompson, Carl V.

Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnect test structures were created by thermocompression bonding, and the bond toughness was measured using a four-point bend test. The effects of bonding temperature, chamber ambient and copper thickness on bond quality were evaluated to optimize the bonding process. A new copper surface cleaning method using glacial acetic acid was employed to obtain high toughness bonds(∼17 J/m2) at low bonding temperatures (<300°C).

Published in:

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Date of Conference:

2-4 June 2003