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90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

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23 Author(s)
Jan, C.-H. ; Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA ; Bielefeld, J. ; Buehler, M. ; Chikamane, V.
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This paper presents a 90 nm generation and 300 mm wafer size interconnect technology with 7 layers of Cu metallization and low k ILD. Carbon doped oxide (CDO) low k ILD is used to achieve > 20% inter- and intra-layer capacitance improvement and 25-30% RC improvement over 130 nm generation SiOF interconnect process with equivalent electromigration performance.

Published in:

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Date of Conference:

2-4 June 2003