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Interprocedural optimizations for improving data cache performance of array-sensitive embedded applications

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4 Author(s)
Zhang, W. ; CSE Dept., Pennsylvania State Univ., University Park, PA, USA ; Chen, Gu. ; Kandemir, M. ; Karakoy, M.

As datasets processed by embedded processors increase in size and complexity, the management of higher levels of memory hierarchy (e.g., caches) is becoming an important issue. A major limitation of most of the cache locality optimization techniques proposed by previous research is that they handle a single procedure at a time. This prevents compilers from capturing the data access interactions between procedures and may result in poor performance. In this paper, we look at loop and data transformations from a different angle and use them in an interprocedural optimization framework. Employing the call graph representation of a given application, the proposed technique visits each node of this graph twice and uses loop and data transformations in a systematic way for optimizing array layouts whole program wide. Our experimental results show that this interprocedural locality optimization strategy is much more effective than the previous locality-based techniques that handle each procedure in isolation.

Published in:

Design Automation Conference, 2003. Proceedings

Date of Conference:

2-6 June 2003