By Topic

Design of a 17-million gate network processor using a design factory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
G. -E. Descamps ; Silicon Access Networks Inc., San Jose, CA, USA ; S. Bagalkotkar ; S. Ganesan ; S. Iyengar
more authors

Silicon Access Networks taped out in one year four high performance SoC products: a high-end network processor and three associated co-processors, providing the industry with the highest performance OC-192 Data Plane Processing solution. The four chips are shipping for revenue and went into production from first silicon with no mask change. They were designed using state-of-the-art 0.13/spl mu/m technology and collectively represent about 750-million transistors, implementing a variety of analog, digital, high-speed memory and functional blocks. This contribution describes the design of the Packet Processor and some of the key aspects of Silicon Access Networks' design methodology that enabled to accomplish repeatable "first pass silicon" successes, despite system complexity challenges. The 175-million transistor iPP was simultaneously designed in three locations (San Jose/CA, Raleigh/NC, Ottawa/Canada). Bring-up and pre-production showed that first silicon met all its targets: power, speed, yield and complete functionality.

Published in:

Design Automation Conference, 2003. Proceedings

Date of Conference:

2-6 June 2003