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On-chip power supply network optimization using multigrid-based technique

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2 Author(s)
Kai Wang ; Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA ; M. Marek-Sadowska

In this paper, we present a multigrid-based technique for on-chip power supply network optimization. We reduce a large-scale network to a much coarser one which can be efficiently optimized. The solution for the original network is then quickly computed using a back-mapping process. We model the power grid by an RLC network and use time-varying current sources to capture the on-chip switching. Our technique is capable of optimizing power grid and decoupling capacitance simultaneously. Experimental results show that the proposed technique provides more robust and are-efficient solutions than those obtained by the earlier approaches. It also provides a significant speed-up and brings up a possibility of incorporating power supply network optimization into other physical design stages such as signal routing.

Published in:

Design Automation Conference, 2003. Proceedings

Date of Conference:

2-6 June 2003