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Cascaded multilevel inverters can be implemented using single-phase modular power bridges, each having their own DSP processor and associated control circuitry. This paper presents details of how these bridges should be operated to synchronise their PWM carriers and fundamental references to implement a cascaded inverter with distributed PWM computation. The paper begins by detailing performance degradations that can occur when phase synchronisation and regular sampling errors exist between the multiple carriers and three-phase references. Details describing the master/slave synchronisation and signal protocols, and timing and sampling considerations to achieve optimum harmonic cancellation and reduced common mode voltage, are then presented to achieve overall optimal system performance. The accuracy and proper synchronisation of the cascaded bridges have been confirmed through the close match between simulation and experimental results obtained using a modular cascaded five-level inverter.