By Topic

A novel control concept for reliable operation of a three-phase three-switch buck-type unity power factor rectifier with integrated boost output stage under heavily unbalanced mains condition

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Baumann, M. ; Inst. of Electr. Drives & Machines, Vienna Univ. of Technol., Austria ; Kolar, J.W.

In this paper the reliable operation of a three-phase three-switch buck-type PWM unity power factor rectifier with integrated boost output stage under heavily unbalanced mains, i.e. mains voltage unbalance, loss of one phase, short circuit of two phases or earth fault of one phase is investigated theoretically and experimentally. The analytical calculation of the relative on-times of the active switching states and of the DC link current reference value is treated in detail for active and deactivated boost output stage. Based on the theoretical considerations a control scheme which allows to control the system for any mains condition without change-over of the control structure is described. Furthermore, digital simulations as well as experimental results are shown which confirm the proposed control concept for different mains failure conditions and for the transition from balanced mains to a failure condition and vice versa. The experimental results are derived from a 5 kW prototype, input voltage range 208-480 Vrms line-to-line, output voltage 400 VDC of the rectifier system, where the control is realized by a 32-bit digital signal processor.

Published in:

Power Electronics Specialist Conference, 2003. PESC '03. 2003 IEEE 34th Annual  (Volume:1 )

Date of Conference:

15-19 June 2003