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Board-level multiterminal net assignment for the partial cross-bar architecture

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6 Author(s)
Xiaoyu Song ; Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA ; Hung, W.N.N. ; Mishchenko, A. ; Chrzanowska-Jeske, M.
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This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 3 )

Date of Publication:

June 2003

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