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High-level synthesis for low power based on network flow method

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2 Author(s)
Chun-Gi Lyuh ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Taewhan Kim

We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems for power optimization can be formulated as network flow problems and cand be solved optimally. However, in these formulations, a fixed schedule was assumed. In such a context, one key problem is that given an optimal network flow solution to a hardware allocation/binding problem for a given schedule, how to generate a new optimal network-flow solution rapidly for a local change of the given schedule. To this end, from a comprehensive analysis of the relation between network structure and flow computation, we devise a two-step procedure: Step 1) a max-flow computation step which finds a valid (maximum) flow solution while retaining the previous (maximum flow of minimum cost) solution as much as possible and Step 2) a min-cost computation step which incrementally refines the flow solution obtained in Step 1, using the concept of finding a negative cost cycle in the residual graph for the flow. The proposed algorithm can be applied effectively to several important high-level optimization problems (e.g., allocations/bindings of functional units, registers, buses, and memory ports) when we have the freedom to choose a schedule that will minimize power consumption. Experimental results (for bus synthesis) on benchmark problems show that our designs are 4%-40% more power-efficient over the designs produced by a random-move based solution and a clock-step based optimal solution, which is due to a) exploitation of the effect of scheduling and b) optimal binding for every schedule instance. Furthermore, our algorithm is about 2.6 times faster in run time over the full network flow based (optimal) algorithm, which is due to c) our novel (two-step) mechanism which utilizes the previous flow solution to reduce redundant flow computations.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:11 ,  Issue: 3 )