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Wafer-scale microdevice transfer/interconnect: from a new integration method to its application in an afm-based data-storage system

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5 Author(s)
M. Despont ; Zurich Res. Lab., IBM Res., Ruschlikon, Switzerland ; U. Drechsler ; R. Yu ; H. B. Pogge
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We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer and interconnect method for batch fabricating system on chip (SOC) that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 freestanding cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel scanning-probe-based data-storage system called the "Millipede". A very high integration density has been achieved even at wafer-scale transfer thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 canti-levers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage media). After device transfer, the system is mechanically and electrically stable up to at least 500 /spl deg/C, allowing post-transfer wafer processing.

Published in:

TRANSDUCERS, Solid-State Sensors, Actuators and Microsystems, 12th International Conference on, 2003  (Volume:2 )

Date of Conference:

8-12 June 2003