A submicrometer CMOS embedded SRAM compiler

A highly flexible memory generation system that produces high-density synchronous single- or dual-port static memories has been developed using a 0.7-μm L_eff CMOS technology. The fully diffused memories are embedded into a gate-array environment. Configurations upwards of 1K words×256 b and 16K words×16 b have been obtained. Single-port address access times are, for example, 6.2 ns for 8K and 6.9 ns for 32K SRAMs. The Memorist SRAM Compiler provides for accurate timing characterization and is tightly integrated into an ASIC design CAD system. A gate-array-based test-chip cluster consisting of four 7.3×7.3 mm dies with 16 embedded diffused memories has also been developed