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Stratified fault sampling is used in register transfer level (RTL) fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault-injection algorithms are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed gate-level stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the gate-level coverage within the statistical error bounds. For a very large scale integration system, consisting of several modules, the level of description may differ from module to module. Therefore, the stratified fault sampling technique is used to determine the overall coverage as a weighted sum of RTL module coverages. Several techniques are proposed to determine these weights, known as stratum weights. For a system timing controller application specific integrated circuit, the stratified RTL coverage of verification test-benches is estimated to be within 0.6% of the actual gate-level coverage of the synthesized circuit. This ASIC consists of 40 modules (consisting of 9000 lines of Verilog hardware description language) that are synthesized into 17,126 equivalent logic gates by a commercial synthesis tool. Similar results on two other systems are reported.