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We describe a property-based test generation procedure for synchronous sequential circuits. Several techniques are used to generate test sequences that achieve high fault coverages at low computational complexity. These include the use of static test compaction, input vector holding with optimal numbers of hold cycles, input vector perturbation, and identification of subsequences that are useful in extending the test sequence. Experimental results presented demonstrate that the proposed procedure achieves fault coverages which are in all cases the same or higher than those achieved by existing procedures.