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This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass ΣΔ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall ΣΔ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-μm CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT ΣΔ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 μW from a single 1.5-V power supply.
Date of Publication: Aug. 2003