By Topic

A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Gerfers, F. ; Inst. of Microsystem Technol., Albert Ludwigs Univ., Freiburg, Germany ; Ortmanns, M. ; Manoli, Y.

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass ΣΔ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall ΣΔ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-μm CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT ΣΔ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 μW from a single 1.5-V power supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 8 )