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A flexible test access mechanism (TAM) for embedded cores and their interconnects in a System-on Chip (SOC) environment is presented. It targets core testing parallelism and reduced test application time while explicitly taking into consideration area and performance issues. The TAM primarily uses core interconnects but also allows for extra interconnects. The DFT hardware can be implemented either at the SOC or at the core level. It combines features of TAMs that have been designed for low test application time and those for SOC area and performance criteria.