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An efficient BIST scheme for high-speed adders

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4 Author(s)
Nikolos, D.G. ; Comput. Eng. & Informatics Dept., Partas Univ., Patras, Greece ; Nikolos, D. ; Vergos, H.T. ; Efstathiou, C.

In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing.

Published in:

On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE

Date of Conference:

7-9 July 2003