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Power-conscious test synthesis and scheduling

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2 Author(s)
Nicolici, N. ; McMaster Univ., Hamilton, Ont., Canada ; Al-Hashimi, B.M.

BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 4 )