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Deterministic BIST for RNS adders

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4 Author(s)
Vergos, H.T. ; Comput. Eng. & Informatics Dept., Patras Univ., Greece ; Nikolos, D. ; Bellos, M. ; Efstathiou, C.

Modulo 2n -1 adders as fast as n-bit 2's complement adders have been recently proposed in the open literature. This makes a residue number system (RNS) adder with channels based on the moduli 2n, 2n - 1, and any other of the form 2k - 1, with k < n, faster than RNS adders based on other moduli. We formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2n, 2n - 1, 2k - 1, 2l - 1, ..., with l < k < n. The derived test set is reusable; it can be used for any value of n, k, l, ..., regardless of the implementation library used and is composed of n2 + 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n2 + 2n cycles. Static CMOS implementations reveal that the proposed BIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.

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Computers, IEEE Transactions on  (Volume:52 ,  Issue: 7 )