By Topic

Variable instruction set architecture and its compiler support

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
J. Liu ; Cognigine Corp., Fremont, CA, USA ; F. Chow ; T. Kong ; R. Roy

A variable instruction set processor provides a dictionary that enables the compiler to configure the best instruction set to use for executing the program being compiled. This paper describes Cognigine's variable instruction set communication architecture (VISC Architecture) and the implementation of a compiler that provides effective compilation and optimization support for this target. The compiler implementation involves the use of an abstract operation representation that enables the code generator to optimize toward the core architecture of the processor without committing to any specific instruction format. It then uses an enumeration approach to instruction scheduling that determines the final forms of the instructions to be generated while still adhering to the irregular constraints imposed by the architecture. The enumeration approach also allows the incorporation of dictionary reuse functionality to provide trade offs between program performance and dictionary budget. Finally, we provide experimental results to show the effectiveness of these compilation techniques in supporting Cognigine's VISC Architecture.

Published in:

IEEE Transactions on Computers  (Volume:52 ,  Issue: 7 )