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Analysis of parallel hierarchical matching schedulers for input-queued switches under different traffic conditions

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3 Author(s)
Gonzalez-Castano, F.J. ; Dep. Ingenieria Telematica, Vigo Univ., Spain ; Lopez-Bravo, C. ; Asorey-Cacheda, R.

Input-queued packet switches are more scalable than output-queued ones. However, due to HOL blocking, their throughput is poor. The virtual output queueing (VOQ) switch architecture and several buffer schedulers have been proposed to overcome this problem. Among them, the class of iterative maximal matching algorithms, with the first example being parallel iterative matching (PIM), which uses random selection, and iSLIP that uses round-robin selection, and has become a de facto standard in switching research. iSLIP admit efficient practical implementations, and has several variants with different pointer updating strategies - like FIRM, DRRM and RDSRR - that improve performance. In previous work, we formulated a new scheduler, parallel hierarchical matching (PHM), which compare favorably to iSLIP-like algorithms. PHM can be considered a parallelization of previous high-performance sequential hierarchical matching algorithms, like 2DRR or WWFA. In this paper, we compare their delay performance for same decision response-time, determined from ASIC implementations, and for different traffic models.

Published in:

Computers and Communication, 2003. (ISCC 2003). Proceedings. Eighth IEEE International Symposium on

Date of Conference:

30 June-3 July 2003