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Multiple-chip module design optimizations using a novel layout parameterization technique

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5 Author(s)
C. -W. P. Huang ; Anadigics Inc., Warren, NJ, USA ; G. S. Dow ; Jianwen Bao ; S. Kuran
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A novel layout parameterization technique for multi-chip module design optimizations is presented. This technique is based on a quasi-static method of moments and multi-dimensional interpolation, which can reduce a 12-minute electromagnetic layout simulation to 5.3 seconds. Excellent CDMA power amplifier (PA) module performance is achieved based on this technique.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

Date of Conference:

8-10 June 2003