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A 2.4GHz dual-modulus divide-by-127/128 prescaler in 0.35 μm CMOS technology

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2 Author(s)
Singh Rana, R. ; Inst. of Microelectron., Singapore, Singapore ; Zhang Chen Jian

High speed design solution for high divide-by-value dual modulus prescaler remains a challenge in designing high frequency synthesizers in CMOS technology. This paper presents a dual-modulus divide-by-127/128 prescaler implemented in 0.35 μm CMOS technology operating at 2.4GHz frequency. Unlike the conventional topologies, this design is based on a novel way of dual-modulus division using four transmission gates in critical path. It consumes 4.8mW power from a 3V supply. Measurement results are provided.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

Date of Conference:

8-10 June 2003

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