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A 1.8 V monolithic CMOS nested-loop frequency synthesizer for GSM receivers at 1.8 GHz

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2 Author(s)
R. Murji ; Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada ; M. Jamal Deen

A low-power, integrated 1.8 GHz nested-loop frequency synthesizer for GSM at 1.8 GHz in a 0.18 μm CMOS technology is presented. The synthesizer consists of two voltage-control oscillators (VCOs) and uses band switching MIM capacitors and analog tuning circuits using pMOS capacitors. Both VCOs and loop-filters are integrated on-chip. The IF VCO phase noise is -131 dBc/Hz@600 kHz from a 450 MHz carrier and the RF VCO phase noise is -121 dBc/Hz@600 kHz from a 1.8 GHz carrier. The power consumption of this nested-loop frequency synthesizer is 36 mW@1.8 V and has a die size of 3000 μm × 2000 μm.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

Date of Conference:

8-10 June 2003