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A 0.8 dB insertion-loss, 23 dB isolation, 17.4 dBm power-handling, 5 GHz transmit/receive CMOS switch

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14 Author(s)
Ohnakado, T. ; Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan ; Yamakawa, S. ; Murakami, T. ; Furukawa, A.
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The highest performance to date of any switch using a CMOS process, with a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using depletion-layer-extended transistors (DETs) in a 0.18 μm CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

Published in:

Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE

Date of Conference:

8-10 June 2003