By Topic

A novel double-recessed 0.2-μm T-gate process for heterostructure InGaP-InGaAs doped-channel FET fabrication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ming-Jyh Hwu ; Dept. of Electr. Eng., Nat. Central Univ., Chungli, Taiwan ; Hsien-Chin Chiu ; Shih-Cheng Yang ; Yi-Jen Chan

A double-recessed T-gate process has been successfully developed to fabricate 0.2-μm gate-length heterostructure InGaP-InGaAs doped-channel FETs (DCFETs) to increase the gate-to-drain breakdown voltage. This technology uses direct electron-beam lithography with a single exposure of a four-layer stack polymethylmethacrylate and polydimethylmethacrylate (photoresists). After the combination of chemical and dry etchings, the double gate-recessed DCFETs exhibit improved DC and RF power performance, as compared with the conventional ones, resulting from the gate-leakage current. The Schottky gate breakdown voltage enhances from 5 to 7 V, and the output power increases from 148 to 288 mW/mm at 5.2 GHz.

Published in:

IEEE Electron Device Letters  (Volume:24 ,  Issue: 6 )