Referenced Items are not available for this document.
A double-recessed T-gate process has been successfully developed to fabricate 0.2-/spl mu/m gate-length heterostructure InGaP-InGaAs doped-channel FETs (DCFETs) to increase the gate-to-drain breakdown voltage. This technology uses direct electron-beam lithography with a single exposure of a four-layer stack polymethylmethacrylate and polydimethylmethacrylate (photoresists). After the combination of chemical and dry etchings, the double gate-recessed DCFETs exhibit improved DC and RF power performance, as compared with the conventional ones, resulting from the gate-leakage current. The Schottky gate breakdown voltage enhances from 5 to 7 V, and the output power increases from 148 to 288 mW/mm at 5.2 GHz.
Published in:
Electron Device Letters, IEEE
(Volume:24
,
Issue:
6
)
Date of Publication: June 2003
- Page(s):
- 381 - 383
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 7701411
- Digital Object Identifier :
- 10.1109/LED.2003.813352
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 22 July 2003
- Issue Date :
- June 2003
- Sponsored by :
- IEEE Electron Devices Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
