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An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems

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2 Author(s)
McBader, S. ; NeuriCam S.p.A, Trento, Italy ; Lee, P.

This paper describes the design of a programmable parallel architecture that is to be used for signal pre-processing in intelligent embedded vision systems. The architecture has been implemented and tested using a Celoxica RC1000 prototyping platform with a Xilinx XCY2000E FPGA. The system operates at a clock rate of 50 MHz and can perform pre-processing functions such as filtering, correlation and transformation on an image of 256x256 pixels at up to 667 frames/s.

Published in:

Parallel and Distributed Processing Symposium, 2003. Proceedings. International

Date of Conference:

22-26 April 2003