By Topic

Efficient FPGA implementation of block cipher MISTY1

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Rouvroy, G. ; Microelectron. Lab., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium ; Standaert, F.-X. ; Quisquater, J.-J. ; Legat, J.

NESSIE is a 3-year research project (2000-2002). The goal of the project is to put forward some algorithms to obtain a set of the next generation of cryptographic primitives. In order to achieve this objective, the project needs to evaluate mathematical security levels and software/hardware implementations. This paper investigates the significance of an FPGA implementation of the block cipher MISTY1. Reprogrammable devices such as FPGA's are highly attractive solutions for hardware implementations of encryption algorithms. A strong focus is placed on a high throughput circuit which completely unrolls all the MISTY1 rounds and pipelines them in order to increase the data rate. Our design allows us to change the plaintext and the key on a cycle-by-cycle basis with no dead cycles. The final core implementation can work at a data rate up to 19.4 Gbps (303 MHz).

Published in:

Parallel and Distributed Processing Symposium, 2003. Proceedings. International

Date of Conference:

22-26 April 2003