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System-level modeling of dynamically reconfigurable hardware with SystemC

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3 Author(s)
Pelkonen, A. ; VTT Electron., Oulu, Finland ; Masselos, K. ; Cupak, M.

To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks have become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects into a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically reconfigurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the reconfigurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows us to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.

Published in:

Parallel and Distributed Processing Symposium, 2003. Proceedings. International

Date of Conference:

22-26 April 2003