By Topic

Massively parallel wireless reconfigurable processor architecture and programming

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

We propose a massively parallel reconfigurable processor architecture targetted for the implementation of advanced wireless communication algorithms featuring matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the space representation of the algorithm in Simulink. The Simulink description is parsed and the algorithm's dependence flow graph is derived, which is scheduled and space-time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable DSP.

Published in:

Parallel and Distributed Processing Symposium, 2003. Proceedings. International

Date of Conference:

22-26 April 2003