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This paper presents a novel architecture for 9/ Discrete Wavelet Transform (DWT) based on Distributed Arithmetic (DA). The proposed architecture optimizes the performance by exploiting the computational redundancy. The DWT inner product of coefficient matrix is distributed over the input by careful analysis of input, output and coefficients word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation processing elements in space domain. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. In the proposed architecture reducing the clock frequency by two or the supply voltage and maintaining the same throughput as of other architecture achieve the low power by a factor of four. The proposed architecture is therefore scalable and can operate at high speed / consumes low power and has reduced computational complexity (improvement of 77.6% over filter based and 40.27% over lifted based architectures) as compared to already published 9/7 biorthogonal wavelet architectures.